Improve Chip Side Wall Crack Issue in Nanometer Packing Process of Semiconductor.

Improve Chip Side Wall Crack Issue in Nanometer Packing Process of Semiconductor.

Assistant Professor    #7270    ccchung@g4e.npust.edu.tw
Year2020
Author, , , 鍾智超, , *
Author count6
Created date2021-09-05
Author order第四(以上)作者
Corresponding author
Publication year2020
Publication month12
Journal nameIEEE Transactions on Components, Packaging and Manufacturing Technology
Publication area阿富汗伊斯蘭國
Volume11
Issue2
Start page173
End page180
Publication type
Review system
LanguageForeign Language